1. Field of Invention
The present invention relates to non-volatile semiconductor memory arrays, and more particularly to NAND EEPROM arrays biased during erase verify to reduce overerase and improve reliability.
2. Related Art
Non-volatile semiconductor memories, such as flash EEPROMs, are well known in the art. Flash EEPROMs typically are transistors comprising source and drain diffusion regions of a first conductivity type (e.g., n-type) formed within a semiconductor substrate of a second conductivity type (e.g., p-type), a polysilicon floating gate overlying a channel region between the source and drain regions, a first insulative layer separating the floating gate from the channel, a polysilicon control gate overlying the floating gate, and a second insulative layer separating the control gate from the floating gate. The flash EEPROM can be programmed, read, or erased by applying different voltages to the transistor.
The EEPROM can be programmed by biasing the control gate to a higher voltage than the substrate. As a result, electrons are accelerated from the substrate across a channel formed between the substrate and floating gate and "tunnel" to the floating gate by Fowler-Nordheim tunneling. The floating gate accumulates and traps the electrons to raise the threshold voltage V.sub.t of the EEPROM. Once programmed, the EEPROM retains the raised threshold voltage.
The EEPROM can be read by applying a read voltage to the control gate of the EEPROM, typically via a word-line, and by applying positive bias to the drain, typically via a bit-line. The read voltage is a voltage below the V.sub.t of a programmed transistor and above the V.sub.t of an erased or unprogrammed transistor. Thus, if the EEPROM is programmed, the transistor will be "off" and not conduct drain current, and if the EEPROM is erased or unprogrammed, the transistor will be "on" and conduct drain current. By sensing this drain current, the EEPROM can be read as storing a "1" or a "0".
The EEPROM can be erased by biasing the substrate to a higher positive voltage than the control gate (e.g., by applying 18 V to the substrate and grounding the control gate) to force the electrons from the floating gate. As a result, the threshold voltage is lowered to a set erased threshold voltage, such as between -1.0 V and -1.5 V.
A well-known non-volatile memory array using this type of flash EEPROM is a NAND array 10 having columns and rows of NAND strings 11, as shown in FIG. 1. Each NAND string 11 consists of N EEPROM transistors 12-1 to 12-N (as described above), where N is typically equal to 8 or 16. Each EEPROM transistor 12, which stores one bit value, is connected serially to other transistors 12 at common drain/source regions, and the string of transistors 12 is connected between a string-select transistor 13 and a ground-select transistor 14. The drain of string-select transistor 13 is connected to a bit-line, and the source is connected to the drain of the first EEPROM transistor 12-1. The drain of ground-select transistor 14 is connected to the source of the last EEPROM transistor 12-N, and the source is connected to an array ground.
A particular transistor, such as transistor 12-2, of NAND string 11 is typically programmed, for example, by applying a program voltage (i.e., 18 V) to the control gate of the selected transistor 12-2, a pass voltage (i.e., 7-10 V) to the control gates of unselected transistors 12, a logic "0" (i.e., 0-0.3 V) to the bit line, a supply voltage V.sub.cc (i.e., 3.3 V) to the gate of string-select transistor 13, and 0 V to the gate of ground-select transistor 14. As a result, string-select transistor 13 is turned on, unselected transistors 12 are turned on to act as pass transistors regardless of their programmed state, and ground-select transistor is turned off. The large voltage difference between the control gate and substrate of selected transistor 12-2 causes Fowler-Nordheim tunneling to raise the threshold voltage of transistor 12-2, thereby programming the desired transistor.
A particular transistor, such as transistor 12-2, is read by applying, for example, a read voltage (i.e., 0 V if the V.sub.t of the erased transistors are negative and the V.sub.t of programmed transistors are positive) and a pass voltage (i.e., 4.5 V) to the control gates of the unselected transistors 12 and string-select and ground-select transistors 13 and 14. As a result, the unselected transistors 12 are turned on and act as pass transistors. A circuit senses if current flows through transistor 12-2, i.e., if transistor 12-2 is turned on, to determine whether a "0" or a "1" is stored.
Transistors 12 of NAND string 11 can be simultaneously erased by applying, for example, a large erase voltage (i.e., 20 V) to the substrate of each transistor 12 and 0 volts to the gate of transistors 12 while floating the gates of select transistors 13 and 14. Due to the large voltage drop, electrons are removed from the floating gates of each transistor 12, thereby shifting the voltage threshold of each transistor negative to erase the transistors.
However, the EEPROM transistors are usually not identical due, in part, to non-uniform process parameters during the fabrication of the transistors. Consequently, even though the same potential is applied during the same erasing operation, the threshold voltages for the transistors may vary, which can result in a range of threshold voltages both below and above the desired erased V.sub.t. When transistors are not properly erased, reading errors may result. For example, an improperly erased transistor having a V.sub.t higher than the read voltage may be mistakenly read as a programmed, rather than an erased, memory cell. During reading, a margin is necessary to minimize effects of read disturb, temperature variations, charge gain, and other adverse effects.
To ensure all transistors are properly erased, a very large or long erase voltage is typically applied to all the transistors. The erase voltage is chosen to be greater than the erase voltage required to erase the worst-case transistor, i.e., the oldest, slowest speed, or highest threshold voltage transistor. Thus, by overerasing the transistors, all transistors are ensured to be erased.
However, problems arise with this type of method. First, by overerasing all the time, fresh memory cells are unnecessarily and repeatedly overdepleted and programmed, thereby reducing the reliability of these cells and increasing these cells' programming times during their lifetime. Second, as the memory cells age, some cells may be increasingly slow to erase so that even with a margin for the erase voltage, some cells may not be guaranteed to properly erase.
Accordingly, a method of ensuring that all the transistors in a NAND string are properly erased is desired that overcomes the deficiencies discussed above with conventional methods.